The objective of the M2 “Integration Circuits and Systems” is to train future researchers or engineers with extensive knowledge and skills in advanced domains of electronic design: hyper-frequencies, components and systems for telecommunications, decananometric microelectronics, microsystems (MEMS/NEMS), analogic and digital embedded systems, conversion AN/NA, signal material treatment, etc. This M2 is based on courses given by 3 establishments considered as references in this domain: Supélec, Télécom ParisTech and Paris-Sud University. The courses will be given on the three corresponding campuses.
Principle job opportunities: Research, R&D in electronics.
The common portion of the training focuses on acquiring fundamental knowledge required to perform high-level activities in analogic and mixed signal electronic design (RF, digital), theoretical as well as practical knowledge (analogic simulation tools, digital simulation/synthesis). The courses given within each of the three M2 specialisations are:
• AMS&RF systems and connected objects
• Analogic/digital integrated circuits
• Circuits and heterogeneous systems that enable students to deal with real design problems, especially via project-type courses and to acquire the associated skills.
At this end of this curriculum, students will have expanded their knowledge and acquired practical know-how that includes mastering the IT design tools most widely used in this area.
Location
ORSAY
GIF SUR YVETTE
PALAISEAU
Career prospects
Following the industry route, this M2 paves the way to a career in research and development; not only in the field of microelectronics, the core of the course, but also more broadly in the design of analogue or digital electronic systems in applications such as embedded systems, sensors, instrumentation or telecommunications.
Following the academic route, this programme leads to thesis preparation not only in microelectronics but also in the various specialisation fields: microsystems, nanoarchitectures, embedded systems, radiofrequency systems, analogue/digital converters, hardware signal processing.
Collaboration(s)
Laboratories
Centre de Nanosciences et de Nanotechnologies
Laboratoire de Génie Electrique et Electronique de Paris.
Laboratoire de Traitement et de Communication de l'Information (LTCI - Télécom ParisTech).
Advanced Analog-to-digital converters and Digital-to-Analog converters (CAN)
Language(s) of instruction :
AN
ECTS :
3
Détail du volume horaire :
Lecture :9
Directed study :3
Practical class :12
Modalités d'organisation et de suivi :
Coordinator :LELANDAIS-PERRAULT Caroline
Pedagogical team :
Coordinator : Caroline Lelandais-Perrault, Maître de conférences, CentraleSupélec Team : Philippe Benabès, Professeur, CentraleSupélec; Patricia Desgreys, Professeur, Télécom Paris.
Procedure and organisation :
9h lectures , 3h of exercises and 12h of practical session.
Objectifs pédagogiques visés :
Contenu :
Objectives :
To understand the technical bottleneck of continuous-time/discrete-time domain interfacing, and the metrics used for characterizing converters. To know the advantages/limitations/applications of the main converter architectures, and have an overview of more advanced architectures. To be able to model, design and simulate an converter in a mixed-signal context.
Contents :
The lectures will recall the theory related to the interface between analog and digital domains, introduce the functions performed by the converters and the metrics used to characterize the converters. The most classic monolithic architectures will be presented as well as advanced conversion techniques based on parallelism. The sigma-delta conversion will also be discussed. A tutorial will focus on the modeling of a Sigma-Delta converter under Matlab. During the project sessions, students will implement an analog-to-digital converter in an integrated technology, under Cadence.
Prerequisites :
M2 level in analog microelectronics equivalent to the "Analog Electronics - Analog Devices and Circuits (EA)" module.
"Lecture 1 (1h30) : Design for Reliability theory
TD 1 (1h30 - exercise) : Design examples under Process-Voltage-Temperature variations
TP 1 (4h30 - practical) : gm over Id characterization
TP 2 (4h30 - practical) : Schematic-level Design
TP 3 (4h30 - practical) : Simulations in design for test, Test Bench unity test
TP 4 (4h30 - practical) : Layout-level Design
TP 5 (4h30 - practical) : Post-layout Simulations, and consistency tests
TP 6 (4h30 - practical) : Monte Carlo Simulations, Voltage and Temperature variations, robustness tests".
Objectifs pédagogiques visés :
Contenu :
- Design for Reliability theory
- Design examples under Process-Voltage-Temperature variations
- gm over Id characterization
- Schematic-level Design
- Simulations in design for test, Test Bench unity test
- Layout-level Design
- Post-layout Simulations,.
Prerequisites :
M2 level in analog microelectronics equivalent to the "Analog Electronics - Analog Devices and Circuits (EA)" module
M2 level in integrated circuits CAD equivalent to the "CAD of Mixed Integrated Circuit (CAD)" module.
Bibliographie :
P. M. Ferreira, J. Ou, C. Gaquière, and P. Benabes, “Automated System-Level Design for Reliability: RF front-end application,” in Computational Intelligence in Electronic Design: AMS/RF Circuit Design, M. Fakhfakh, E. Tlelo-Cuautle, and P. Siarry, Eds. Springer, 2015, pp. 363–389.
P. M. Ferreira, H. Cai, and L. Naviner, “Reliability Aware AMS / RF Performance Optimization,” in Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, M. FAKHFAKH, E. Tlelo-Cuautle, and M. H. S. Fino, Eds. IGI-Global, 2014, pp. 28–54.
Coordinator : Philippe Benabes, Professeur, CentraleSupélec Team : Hervé Mathias, Maître de conférences CNU 63, Université Paris-Sud Caroline Lelandais-Perrault, Maître de Conférences, Centrale Supélec.
Procedure and organisation :
7,5h lectures and 7,5h exercises in parallel at the beginning and then 9h mini-project (practical work).
Objectifs pédagogiques visés :
Contenu :
Objectives :
To have an overview of VHDL-based design methods for simple digital systems, and to master the design flow (description, simulation, logic synthesis), and the implementation and programming on an FPGA board.
Contents :
- Lectures on the architecture and design of digital systems
- Lectures on VHDL-based design, modeling and synthesis
- Tutorials on VHDL
- A design project on the implementation of a digital function on an FPGA.
Prerequisites :
M1 level in digital circuit design
Basic knowledge of a Hardware description language.
24h lectures, 4,5h exercises and 12h practical work.
Objectifs pédagogiques visés :
Contenu :
Objectives :
The objective is to make the students familiar with the main techniques of implementing HW operators, improving their performance and saving costs. The operators covered are those typically used in digital signal/image processing.
Contents :
This course deals with hardware implementation for dedicated computing. High-quality implementation involves trade-off between cost and performance so as to better meet target application requirements and technology constraints.
Prerequisites :
M2 level in digital circuit design equivalent to the "Digital Electronics 1 - Digital systems (EN1)" module.
Coordinator : Emilie Avignon, Maître de conférences, CentraleSupélec Team : Philippe Benabès, Pietro Maris, CentraleSupélec.
Procedure and organisation :
3h lecture at the beginning and then 21h practical work.
Objectifs pédagogiques visés :
Contenu :
Objectives :
To obtain basic knowledge of the design of analog integrated circuits. To understand the specificities, limitations and future of integrated technologies. To master all the steps of the design-flow of an analog integrated circuit.
Contents :
During this course, through the top-down approach of a complete analog architecture (from high-level blocks to the layout), the student will learn the Cadence tool for simulation, layout and verifications (DRC, LVS, extraction and post-layout simulations). Students will also be able to use automatic tools for the layout of digital circuits.
Prerequisites :
M2 level in Analog integrated circuits equivalent to the "Analog Electronics - Analog Devices and Circuits (EA)" module.
Cell Design For Digital Integrated Circuits (CD2IC)
Language(s) of instruction :
AN
ECTS :
3
Détail du volume horaire :
Lecture :15
Practical class :13.5
Modalités d'organisation et de suivi :
Coordinator :MATHIEU Yves
Pedagogical team :
Coordinators : Yves Mathieu, Professeur, Telecom Paris , Chadi Jabbour, Maître de conférences, Telecom Paris, Team : Damien Querlioz, Chargé de recherche, CNRS.
Procedure and organisation :
15h lectures and 13,5h of practical work.
Objectifs pédagogiques visés :
Contenu :
Objectives :
• Make students aware of the issues related to the design of digital integrated circuits and teach techniques to develop full-custom digital ASIC
• Learn methods to design and optimize logic gates: performance/size/consumption/timing tradeoffs at transistor level
• Present tools allowing to automate mask drawing
• Present future technical evolutions and their impact on the design of digital components.
Prerequisites :
M1 level in digital circuits design
M1 level in CMOS technology.
Coordinator : Patricia Desgreys, Professeur, Télécom Paris (TP) Team : Chadi Jabbour (MdC TP), Germain Pham (IR TP), Paul Chollet (MdC, TP), Jean-Christophe Cousin (MdC, TP).
Procedure and organisation :
Base concept in RF design (1,5h lesson)
RF Transceiver architecture (1,5h lesson)
Diplexer, antenna & PA for Front End RF (3h lesson)
S Parameters (3h lesson)
Digital modulations (3h lesson, 1,5h exercise)
Filtering (3h lesson, 3h WP)
Frequency synthesis (1,5h lesson, 1,5h exercise)
RF Front-end simulation (3h WP)
Transceivers Specifications (3h lesson).
Objectifs pédagogiques visés :
Contenu :
Objectives :
Introduce the concepts, the architectures and basic components of frontend RF transceiver. The indispensable analogue functions are identified and studied in detail : RF components, frequency synthesis and Filtering.
Contents :
• Basic concepts in RF design
• Architectures of RF transceivers
• Transceiver sizing
• Frontend RF components
• Linear digital modulations and spectral efficiency
o Impact of RF imperfections – Performance analysis
o Frequency synthesis
o S Parameters
o Analogue filtering.
Prerequisites :
Basic knowledge in analog electronics :
active and passive components, mathematical modeling,
Main analog functions: amplifying, filtering, conversion.
Bibliographie :
Behzad Razavi, RF Microelectronics
Franco Maloverti, Data converters.
Coordinator : Jérôme Juillard, professeur, Centrale Supélec.
Procedure and organisation :
3h lectures at the beginning followed by 21h of practical work.
Objectifs pédagogiques visés :
Contenu :
Objectives :
To learn the skills required for (i) modeling multiphysical devices coupled with electronics, and (ii) integrating them in a co-design flow.
Contents :
- lecture on fundamentals of MEMS energy harvesters (1h30) - lecture on VHDL-AMS, as a standard tool for multi-physics / analog modeling (1h30) design and modeling of a MEMS kinetic energy harvester for vibration monitoring applications (7*3h lab).
Mixed-signal, Analog & RF Systems for communicating objects (SMART)
Language(s) of instruction :
AN
ECTS :
3
Détail du volume horaire :
Lecture :24
Directed study :1.5
Practical class :3
Modalités d'organisation et de suivi :
Coordinator :DESGREYS Patricia
Pedagogical team :
Coordinator : Patricia Desgreys, Professeur, Télécom Paris Team : Ph. Martins (TP) Christophe Roblin (MdC, TP), Jean-Christophe Cousin (MdC, TP), Chadi Jabbour (MdC, TP), Lirida Naviner (Pr, TP), Germain Pham (IR, TP), Paul Chollet (MdC, TP) + Persons from the industry.
Procedure and organisation :
LTE Physical layer & Introduction to 5G (3h lesson)
Evolution of cellular systems architecture: from 2G to 5G (3h lesson)
Modern antennas (3h lesson)
Adaptative RF filtering : Npath filter (1,5h lesson, 1,5h exercise)
Reliability (3h lesson)
Wireless Transceiver Architecture (3h lesson)
Smart ADCs (3h lesson)
PA linearization (1,5h lesson, 3h WP)
Adaptive Compressive Sensing for Radio-Frequency Receivers(3h lesson).
Objectifs pédagogiques visés :
Contenu :
Objectives :
This teaching presents, from the radio communication standard data, how to choose the overall hardware architecture of a transmitter or a receiver, how to specify the characteristics of the chain elements, how to model at behavioral level and how to design baseband functions. Examples are shown for the 5G and the Internet of Things.
Contents :
• Cognitive radio
• RFM, Baseband
• Digital signal processing
• RF receivers architectures
• System in Package
o Low-Power Design
o Reliability
o Digitizing Analog Systems
o Designing CMOS Wireless System-on Chip.
Prerequisites :
Concepts, architectures and basic
components of frontend RF transceiver.
Bibliographie :
C. Jabbour, P. Desgreys and D. Dallet, Digitally Enhanced Mixed Signal Systems, IET The Institution of Engineering and Technology, June 2019.
Coordinateur : Pietro MARIS FERREIRA, CentraleSupelec ; Team : Emilie AVIGNON-MESELDZIJA , CentraleSupelec ; Jean-Paul Kleider, CNRS.
Procedure and organisation :
Lecture 1-3 (1h30) : Semiconductor Physics theory
TD 1 (1h30) : Semiconductor Physics examples and applications
Lecture 4 (1h30) : MOS transistor models in WI and SI, e.g. UCM and gm over Id methodologies
Lecture 5 (1h30) : Single stage amplifier design theory
TD 2 (1h30) : Single stage amplifier design examples
Lecture 6 (1h30) : 2-stage amplifier design theory (OTA Miller, folded cascode)
TD 3 (1h30) : 2-stage amplifier design examples
TP 1 (1h30 - practical) : Amplifier Simulation using CADENCE
Lecture 7 (1h30) : Design of Comparators, Sample and Hold, Transmission gates
TD 4 (1h30) : Comparators design examples
Lecture 8/TD 5 (3h) Analog Circuit Architectures: Gm-C synthesis, gyrators, delay lines; theory and examples
Lecture 9 /TD 6 (3h) : Physical design and layout constraints; theory and examples
Lecture 10 (1h30) : Noise models and sources of noise
TD 7 (1h30) : Noise analysis of electronic circuits
TP 2 (1h30 - practical) : Lab Exam : Simulations using CADENCE
Exam (1h30) : Written Exams.
Objectifs pédagogiques visés :
Contenu :
- Semiconductor Physics theory
- Semiconductor Physics examples and applications
- MOS transistor models in WI and SI, e.g. UCM and gm over Id methodologies
- Single stage amplifier design theory
- Single stage amplifier design examples
- 2-stage amplifi.
Prerequisites :
Master 1 Diploma in Electronics/Microelectronics or equivalent.
Bibliographie :
S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Jonh Wiley ’Sons, 1981.
T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd ed. Danvers, MA: John Wiley & Sons, Inc., 2012.
B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw Hill, 2003.
Circuit nanoarchitecture and deep learning (NARCHI)
Language(s) of instruction :
AN
ECTS :
3
Détail du volume horaire :
Lecture :16
Practical class :12
Modalités d'organisation et de suivi :
Coordinator :QUERLIOZ Damien
Pedagogical team :
Coordinator : Damien Querlioz, Chargé de recherche, CNRS Team : Jacques-Olivier Klein, Professeur des universités CNU 63, Université Paris-Saclay.
Procedure and organisation :
16h lectures followed by 12h practical work.
Objectifs pédagogiques visés :
Contenu :
Objectives :
- Discovering the new electronic devices obtained using nanotechnologies and the associated problems linked to their use.
- Studying a pre-industrial case : integration of new non-volatile memories with CMOS technology.
- Studying a research case : new bio-inspired paradigms for nanodevices exploitation.
Contents :
nanodevices for microelectronics :
- More Moore devices (FinFET and FDSOI) - Beyond CMOS devices(graphene, nanotubes/nanowires?)
- More Than Moore devices (non-volatile memories, energy havesting, sensors)
Focus 1 : embedded non-volatile memories (preindustrial case)
- New resistive memories thanks to nanotechnologies : magnetic (MRAM), phase changing (PCM) and resistive (RRAM, CBRAM)
- Standalone and embedded applications
- choice of project : circuits design for non-volatile processor (recommended to M2 ICS Students) or sizing and design of memory cells (recommended to students of M2 Nanosciences without CMOS design experience) Focus 2 : bioinspired nanoelectronics (research case)
- Biology as a model of extreme energetic efficiency.
- Bioinspired nanoelectronics examples
Practical : simulation of a neuromorphic circuit with memristors.
Objectives :
To be confronted with a concrete research problem in the domain of IC Design.
Contents :
Literature review and research work, which may include theoretical, technical, practical or/and software aspects.
Période(s) et lieu(x) d’enseignement :
Period(s) :
Janvier - Février - Mars.
Location :
ORSAY - GIF-SUR-YVETTE - PALAISEAU
Modalités de candidatures
Application period
From 15/01/2024 to 07/07/2024
Compulsory supporting documents
Rank of previous year and size of the promotion.
Motivation letter.
All transcripts of the years / semesters validated since the high school diploma at the date of application.
Certificate of English level (compulsory for non-English speakers).
(Mandatory if english not native language)
Curriculum Vitae.
Detailed description and hourly volume of courses taken since the beginning of the university program.
Additional supporting documents
VAP file (obligatory for all persons requesting a valuation of the assets to enter the diploma).
The application procedure, which depends on your nationality and your situation is explained here : https://urlz.fr/i3Lo.
Supporting documents :
- Residence permit stating the country of residence of the first country
- Or receipt of request stating the country of first asylum
- Or document from the UNHCR granting refugee status
- Or receipt of refugee status request delivered in France
- Or residence permit stating the refugee status delivered in France
- Or document stating subsidiary protection in France or abroad
- Or document stating temporary protection in France or abroad.
